work / aurascope / step 13

STEP 13 · TAG v1.2-pl-i2s-rx

PL I2S RX logic (bonus)

// phase 5 · advanced (bonus) · status: planned · published [date]

The goal of this step

Build minimal HDL receive logic in the Zynq PL; wire nRF I2S into the fabric.

What I did

The tricky part

[ The one thing that actually cost time. Be specific and honest — this is the section readers remember. ]

# [ the handful of commands / code that matter — keep it copy-pasteable ]
Honest note: [ anything simulated, stubbed, or deferred at this stage — state it plainly. ]

Result

[ The concrete, verifiable win for this step, and what it unlocks for the next one. ]

Code

Tagged at v1.2-pl-i2s-rx.